Measurement Computing PCM-DAS16D/12 - Manual (Page 32)

COUNTER SECTION
Counter type 82C54
Configuration 3 down counters, 16 bits each
Counter 0 - User counter 1
Source: Programmable external (Ctr 1 Clk)
or 100kHz internal source
Gate: Available at connector (Ctr 1 Gate)
Output: Available at connector (Ctr 1 Out)
Counter 1 - ADC Pacer Lower Divider
Source: Programmable, 1MHz or 10 MHz
internal source
Gate: Available at connector (Ctr 2 Gate),
pulled to logic high through 10k
resistor
Output: Chained to Counter 2 Clock
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output
Gate: Programmable, external (Ext
Trig/Clk) or Not Connected (pulled
high through 10k resistor)
Output: Programmable as ADC Pacer clock,
hard-wired to user connector (Ctr 3
Out)
Clock input frequency 10 Mhz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
28