1 my talk address – Measurement Computing Digital488 User Manual
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Section 2
Getting Started
2.10
2.4.1 My Talk Address (MTA)
When the Digital488 is addressed to talk (R0) it asserts Inhibit, reads
the data from all ports, un-asserts Inhibit and outputs the data to the bus in
the format as defined by the Fn, Pn and Gn commands. The output bus
terminators are appended to the output with the exception of the F4 and F5
formats. F4 does not append terminators. The output format of F5 will be
described separately. After output in the F0 through F4 formats, the
Digital488 must be re-addressed to talk to perform subsequent reads.
In the R1 mode, it will wait for the selected EDR transition before
reading the data and formatting it for output. If the EDR line has transitioned
prior to being addressed to talk, the data read at the time of EDR will be
buffered for output when next addressed to talk. If EDR transitions again
before the previous EDR buffered data has been output, the Digital488 will
generate an EDR Overrun error and ignore the EDR read request. After
output in the F0 through F4 formats, the Digital488 must be re-addressed to
talk to perform subsequent buffered output of EDR captured data.
In either Rn mode, the Digital488 can send requested status (Un)
without affecting the data ports or Inhibit. After the requested status is
output, the presently programmed Rn mode returns.
EDR cannot be used to capture data in the high speed binary format
(F5). When addressed to talk in this format it asserts Inhibit, reads the data
from all ports, un-asserts Inhibit and outputs the binary data to the bus with
EOI asserted on the fifth byte. When the last data byte is transferred, the data
is read again in anticipation of another data transfer. If Inhibit is used to
sequence external hardware, this line will pulse N+1 times; where N is the
number of total (5 byte) data transfers. In this format the Digital488 does not
have to be re-addressed to talk to read the ports multiple times.
With all Fn formats, the data is output in a PORT5, PORT4, PORT3,
PORT2, PORT1 sequence.