Measurement Computing COM232/8AT - Manual (Page 13)

1000-0901, rev 1.1 March 1998 COM232/8AT User’s Guide 13
Line Status Register
The bit definitions for the Line Status Register are as follows:
Line Status Register Definitions
D7 FFRX Error in FIFO RCVR (FIFO only)
D6 TEMT Transmitter Empty
D5 THRE Transmitter Holding Register Empty
D4 BI Break Interrupt
D3 FE Framing Error
D2 PE Parity Error
D1 OE Overrun Error
D0 DR Data Ready
FFRX FIFO Receiver Error − Always logic 0 when in the 16550 character mode. FIFO Mode −
Indicates one or more parity errors, framing errors, or breaks in the receiver FIFO. FFRX is reset by
reading the Line Status Register.
TEMT Transmitter Empty − Indicates the transmitter holding register (or FIFO) and the transmitter
shift register are empty and are ready to receive new data. TEMT is reset by writing a character to the
Transmitter Holding Register.
THRE Transmitter Holding Register Empty − Indicates the Transmitter Holding Register (or FIFO) is
empty and is ready to accept new data. THRE is reset by writing data to the Transmitter Holding
Register.
Note: This note pertains to the bits BI, FE, PE, and OE. These bits are sources of receiver line
status interrupts. The bits are reset by reading the Line Status Register. In FIFO mode, each
bit is associated with a specific character in the FIFO and the exception is revealed only when
that character reaches the top of the FIFO.
BI Break Interrupt − Indicates the received data input has been in the spacing state (logic 0) for longer
than the transmission time of one full word. FIFO Mode − Only one zero character is loaded into the
FIFO and transfers are disabled until SIN goes to the mark state (logic 1) and a valid start bit is
received.
FE Framing Error − Indicates the received character had an invalid stop bit. The stop bit following
the last data or parity bit was a 0 bit (spacing level).
PE Parity Error − Indicates the received data does not have the correct parity.
QE Overrun Error − Indicates the receive buffer was not read before the next character was received.
The character is destroyed. FIFO Mode − Indicates the FIFO is full and another character has been
shifted in. The character in the shift register is destroyed, but is not transferred to the FIFO.
DR Data Ready − Indicates data is present in the receive buffer (or FIFO). DR is reset by reading the
Receive Buffer Register.