Foxconn C51XEM2AA-8EKRS2H - Manual (Page 43)

Chapter 3 BIOS Description
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v tRAS
Minimum RAS# active time
v Command Per Clock (CMD)
Command timing setting (per clock unit).
Advance Memory Settings
v tRRD
RAS# to RAS# delay of different banks.
v AsyncLat
Max round trip latency from the CPU to the DRAM.
v tRC
RAS# to RAS# or auto refresh time of the same bank.
v tWR
Write recovery time.
v tRWT
Minimum read to write turnaround time.
v tWTR
Minimum write to read delay with same chip select.
v tREF
DRAM refresh rate.
v Read DQS Skew
Read DQS delayed with respect to the data. 1/96 MEMCLK per unit.
v Read delay from Rx FIFO
Delay from DQS receiver enable to first data read from Rx FIFO.
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