Digi NS9210 User Manual
Page 26
26
NS9210 Processor Module Hardware Reference
C h a p t e r 1
Changing the
CPU speed
After powerup, software can change the PLL settings by writing to the PLL
configuration register (@ 0xA090_0188)
Important:
When PLL parameters are changed, a reset is provided for the PLL to
stabilize. Applications using this feature need to
be aware the SDRAM contents will be
lost. See reset behavior in the table below.
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B o o t p r o c e s s
The NS9210 Processor Module boots directly from NOR flash. The start-up code is
located at address 0x00000000 during the boot process. When the system is booted,
the SDRAM is remapped to address 0x00000000 and Nor Flash to 0x50000000 by
modifying the address map in the AHB decoder.
CPU clock = 299.8272 MHz / 2 = 149.9136 MHz
AHB clock = 149.9136 MHz / 2 = 74.9568 MHz
Reset Behavior
RESET
_n pin
SRESET
_n pin
PLL
Config
Reg.
Update
Watchdog
Time-Out
Reset
SPI boot
YES
YES
YES
YES
Strapping PLL
YES
NO
NO
NO
Other strappings (Endianess)
YES
NO
NO
NO
GPIO configuration
YES
NO
NO
NO
Other (ASIC) registers
YES
YES
YES
YES
SDRAM keeps its contents
NO
YES
NO
YES