4 commands, 5 address modes, 6 interrupt request register (al event register) – BECKHOFF ET1200 User Manual
Page 46: Commands, Address modes, Interrupt request register (al event register), Table 39: spi commands cmd0 and cmd1, Table 40: address modes, Table 41: interrupt request register transmission
PDI Description
III-36
Slave Controller
– ET1200 Hardware Description
6.3.4
Commands
The command CMD0 in the second address/command byte may be READ, WRITE, NOP, or Address
Extension. The command CMD1 in the third address/command byte may have the same values:
Table 39: SPI commands CMD0 and CMD1
CMD[2]
CMD[1]
CMD[0]
Command
0
0
0
NOP (no operation)
0
0
1
reserved
0
1
0
Read
0
1
1
reserved
1
0
0
Write
1
0
1
reserved
1
1
0
Address Extension (3 address/command bytes)
1
1
1
reserved
6.3.5
Address modes
The SPI slave interface supports two address modes, 2 byte addressing and 3 byte addressing. With
two byte addressing, the lower 13 address bits A[12:0] are selected by the SPI master, while the upper
3 bits A[15:13] are assumed to be 000b inside the SPI slave, thus only the first 8 Kbyte in the
EtherCAT slave address space can be accessed. Three byte addressing is used for accessing the
whole 64 Kbyte address space of an EtherCAT slave.
Table 40: Address modes
Byte
2 Byte address mode
3 Byte address mode
0
A[12:5]
address bits [12:5]
A[12:5]
address bits [12:5]
1
A[4:0]
address bits [4:0]
CMD0[2:0] read/write command
A[4:0]
address bits [4:0]
CMD0[2:0] 3 byte addressing: 110b
2
D0[7:0]
data byte 0
A[15:13]
address bits [15:13]
CMD1[2:0] read/write command
res[1:0]
two reserved bits, set to 00b
3
D1[7:0]
data byte 1
D0[7:0]
data byte 0
4 ff.
D2[7:0]
data byte 2
D1[7:0]
data byte 1
6.3.6
Interrupt request register (AL Event register)
During the address phase, the SPI slave transmits the PDI interrupt request registers 0x0220-0x0221
(2 byte address mode), and additionally register 0x0222 for 3 byte addressing on SPI_DO (MISO):
Table 41: Interrupt request register transmission
Byte
2 Byte address mode
3 Byte address mode
SPI_DI
(MOSI)
SPI_DO
(MISO)
SPI_DI
(MOSI)
SPI_DO
(MISO)
0
A[12:5]
I0[7:0]
interrupt request
register 0x0220
A[12:5]
I0[7:0]
interrupt request register
0x0220
1
A[4:0]
CMD0[2:0]
I1[7:0]
interrupt request
register 0x0221
A[4:0]
CMD0[2:0]
I1[7:0]
interrupt request register
0x0221
2
(Data phase)
A[15:13]
CMD1[2:0]
I2[7:0]
interrupt request register
0x0222