BECKHOFF EtherCAT Technology Section I - Manual (Page 115)

Additional Information
Slave Controller – Technology I-95
17.3 Write Protection
Some ESCs are capable of register write protection or entire ESC write protection.
Registers used for write protection are described in Table 60:
Table 60: Registers for Write Protection
Register Address Name Description
0x0020 Register Write Enable Temporarily release register write protection
0x0021 Register Write Protection Activate register write protection
0x0030 ESC Write Enable Temporarily release ESC write protection
0x0031 ESC Write Protection Activate ESC write protection
NOTE: Some of these registers are not available in specific ESCs. Refer to Section II for details.
17.3.1 Register Write Protection
With register write protection, only the register area 0x0000 to 0x0F7F is write protected (except for
registers 0x0020 and 0x0030). User RAM (0x0F80:0x0FFF) and Process Data RAM (0x1000:0xFFFF)
are not protected.
If register write protection is enabled (register 0x0021[0]=1), the Register Write Enable bit (0x0020[0])
has to be set in the same frame before any register write operations. This is also true for disabling the
register write protection. Otherwise, write operations to registers are discarded.
17.3.2 ESC Write Protection
ESC write protection disables write operations to any memory location (except for registers 0x0020
and 0x0030).
If ESC write protection is enabled (register 0x0031[0]=1), the ESC Write Enable bit (0x0030[0]) has to
be set in the same frame before any write operations. This is also true for disabling the ESC write
protection as well as the register write protection. Otherwise, write operations are discarded.
NOTE: If both register write protection and ESC write protection are enabled (not recommended), both enable bits
have to be set before the write operations are allowed.
17.4 ESC Reset
Some ESCs are capable of issuing a hardware reset by the EtherCAT master or even via the PDI. A
special sequence of three independent and consecutive frames/commands has to be sent to the slave
(Reset register ECAT 0x0040 or PDI 0x0041). Afterwards, the slave is reset.
NOTE: It is likely that the last frame of the sequence will not return to the master (depending on the topology),
because the links to and from the slave which is reset will go down.