BECKHOFF EtherCAT Technology Section I - Manual (Page 10)

TABLES
I-X Slave Controller – Technology
TABLES
Table 1: ESC Main Features ................................................................................................................... 1
Table 2: EtherCAT Frame Header........................................................................................................... 4
Table 3: EtherCAT Datagram .................................................................................................................. 6
Table 4: EtherCAT Addressing Modes .................................................................................................... 6
Table 5: Working Counter Increment ...................................................................................................... 8
Table 6: EtherCAT Command Types .................................................................................................... 10
Table 7: EtherCAT Command Details ................................................................................................... 11
Table 8: Registers for Loop Control and Loop/Link Status ................................................................... 13
Table 9: Frame Processing Order ......................................................................................................... 14
Table 10: Link Status Description .......................................................................................................... 17
Table 11: Registers for Enhanced Link Detection ................................................................................. 18
Table 12: Registers for FIFO Size Reduction ........................................................................................ 19
Table 13: Special/Unused MII Interface signals .................................................................................... 21
Table 14: Registers used for Ethernet Link Detection ........................................................................... 22
Table 15: PHY Address configuration matches PHY address settings ................................................. 27
Table 16: PHY Address configuration does not match actual PHY address settings ........................... 27
Table 17: MII Management Interface Register Overview ...................................................................... 28
Table 18: MII Management Interface timing characteristics .................................................................. 29
Table 19: Signals used for Fast Ethernet .............................................................................................. 32
Table 20: EBUS Interface signals ......................................................................................................... 35
Table 21: EBUS timing characteristics .................................................................................................. 36
Table 22: Example FMMU Configuration .............................................................................................. 39
Table 23: SyncManager Register overview ........................................................................................... 41
Table 24: EtherCAT Mailbox Header .................................................................................................... 44
Table 25: Registers for Propagation Delay Measurement .................................................................... 50
Table 26: Parameters for Propagation Delay Calculation ..................................................................... 53
Table 27: Registers for Offset Compensation ....................................................................................... 55
Table 28: Registers for Resetting the Time Control Loop ..................................................................... 56
Table 29: Registers for Drift Compensation .......................................................................................... 57
Table 30: Reference between DC Registers/Functions and Clocks ..................................................... 58
Table 31: Distributed Clocks signals ..................................................................................................... 60
Table 32: SyncSignal Generation Mode Selection ................................................................................ 61
Table 33: Registers for SyncSignal Generation .................................................................................... 62
Table 34: Registers for Latch Input Events ........................................................................................... 65
Table 35: Registers for the EtherCAT State Machine ........................................................................... 71
Table 36: AL Control and AL Status Register Values ........................................................................... 71
Table 37: ESC Configuration Area ........................................................................................................ 73
Table 38: SII EEPROM Content Excerpt ............................................................................................... 74
Table 39: SII EEPROM Interface Register Overview ............................................................................ 74
Table 40: SII EEPROM Interface Errors ................................................................................................ 75
Table 41: I²C EEPROM signals ............................................................................................................. 78
Table 42: EEPROM Size ....................................................................................................................... 78
Table 43: I²C Control Byte ..................................................................................................................... 79
Table 44: I²C Write Access .................................................................................................................... 79
Table 45: I²C Read Access .................................................................................................................... 80
Table 46: EEPROM timing characteristics ............................................................................................ 80
Table 47: Registers for AL Event Request Configuration ..................................................................... 82
Table 48: Registers for ECAT Event Request Configuration ................................................................ 83
Table 49: Registers for Watchdogs ....................................................................................................... 84
Table 50: Error Counter Overview ......................................................................................................... 85
Table 51: Errors Detected by Physical Layer, Auto-Forwarder, and EtherCAT Processing Unit ......... 86
Table 52: RUN LED state indication ...................................................................................................... 87
Table 53: Registers for RUN LED control ............................................................................................. 87
Table 54: Automatic ESC ERR LED state indication ............................................................................ 88
Table 55: Registers for ERR LED control .............................................................................................. 88
Table 56: LINKACT LED States ............................................................................................................ 89
Table 57: Available PDIs depending on ESC ........................................................................................ 91
Table 58: Functions/registers affected by PDI register function acknowledge by write ........................ 92
Table 59: ESC Power-On Sequence ..................................................................................................... 94
Table 60: Registers for Write Protection ............................................................................................... 95