Zilog EZ80F91 - Manual (Page 73)

eZ80F91 Development Kit
User Manual
UM014220-0508 Appendix A—General Array Logic Equations
68
//expansion module
//Flash enabled if this is 0
//wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);
wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them
//is 0 Flash is
//disabled
assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN : ~(nEX_FL_DIS);
assign nL_RD =
~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0)|(nEM_EN=
=0)|(nCS_EX==0));
assign nmemen4 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h17));
assign nmemen3 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h16));
assign nmemen2 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h15));
assign nmemen1 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h14));
assign nEM_EN =
~((nCS2==0)&({A7,A6,A5,A4,A3,A2,A1,A0}==8'h80));
endmodule
U15 Address Decoder
`define anode 8'h00
`define cathode 8'h01
`define latch 8'h02
// FOR eZ80 Development Platform Rev B
// This PAL generates signals that control Expansion
// Module access, LED and Port A emulation
// This device is a GAL22LV10-5JC (5ns tpd) or
// equivalent with Package = 28 pin PLCC