Table 7 – Zilog EZ80F91 User Manual
Page 26
eZ80F91 Development Kit
User Manual
UM014220-0508
eZ80 Development Kit
21
PC[7:0]
39,41,43,
45,47,49,
51,53
Port C, Bit [7:0]
IN/OUT
ID_[2:0]
6,8,10
eZ80Acclaim!
Development Kit
ID
OUT
CON_DIS
12
Console Disable
IN
If a shunt is installed between
pins 12 and 14, the Console
function on the eZ80Acclaim!
Development Kit is disabled.
Reserved
16,18
PD[7:0]
22,24,26,
28,30,32,
34,36
Port D, Bit[7:0]
IN/OUT
PB[7:0]
40,42,44,
46,48,50,
52,54
Port B, Bit[7:0]
IN/OUT
Note: *All of the signals are driven directly by the CPU.
Table 7. CPU Bus Connector J8*
Signal
Pin #
Function
Direction
A[0:7]
3–10
Address Bus, Low Byte
OUT
A[8:15]
13–20
Address Bus, High Byte
OUT
A[16:23]
23–30
Address Bus, Upper Byte
OUT
RD
33
READ Signal
OUT
RESET
35
Push Button Reset
OUT
Table 6. GPIO Connector J6* (Continued)
Signal
Pin #
Function
Direction
Notes