Zilog EZ80F91 - Manual (Page 27)

eZ80F91 Development Kit
User Manual
UM014220-0508 eZ80 Development Kit
22
I/O Functionality
The eZ80Acclaim!
®
Development Kit provides I/O functionality. These
functions are memory-mapped with an address decoder based on the
Generic Array Logic GAL22lV10D (U15) device manufactured by Lat-
tice Semiconductor, and a bidirectional latch (U16). Additionally, U15 is
used to decode addresses for access to the 7 x 5 LED matrix.
Table 8 lists the addresses of registers that allow access to the above func-
tions. The register at address 800000h controls GPIO Output Control and
LED Anode register functions. The register at address 800001h controls
the register functions for the LED cathode, modem reset, and user triggers.
Address
800002h contains GPIO data.
BUSACK 37 CPU Bus Acknowledge Signal OUT
NMI 39 Nonmaskable Interrupt IN
D[0:7] 43–50 Data Bus IN/OUT
CS[0:3] 53–56 Chip Selects
MREQ 57 Memory Request OUT
WR 34 Write Signal OUT
INSTRD 36 Instruction Fetch OUT
BUSREQ 38 CPU Bus Request signal
PHI 40 Clock output of the CPU OUT
Note: *All of the signals except BUSACK and INSTRD are driven by low-voltage CMOS technology
(LVC) drivers.
Table 7. CPU Bus Connector J8* (Continued)
Signal Pin # Function Direction