Zilog EZ80F91 - Manual (Page 49)

eZ80F91 Development Kit
User Manual
UM014220-0508 eZ80F91 Module
44
Essentially, after the eZ80F91 device accesses Flash memory, a time
duration of 8.8 ns + 25 ns = 33.8 ns can transpire before Flash memory
stops driving the data bus. At that time, the eZ80F91 device is well into
the next bus cycle. Assuming this next cycle is the Memory Write cycle,
then the data output of the eZ80F91 device is valid not later than T3 = 7.5
ns, and the write pulse is asserted not later than 4.5 ns after the falling
edge of the CPU Clock (14.5 ns from the rising edge if the CPU Clock is
50 MHz). The duration of bus contention, T
CON,
is 33.8 ns – 7.5 ns =
26.3 ns. Refer to the External Memory Write Timing diagram in the
eZ80F91 Product Specification (PS0192) for assistance.
With the addition of a Fast buffer, Flash turn-off time is reduced from 25
ns to 5.5 ns. Bus contention can still occur, but the amount of time it con-
sumes is not T
CON
= 26.3 ns but rather T
CON
= (8.8 ns – 7.5 ns + 5.5 ns)
= 6.8 ns. At this faster rate, data that is being written does not become
corrupted because the write pulse is not yet asserted.
As of the date of publication of this document, Zilog has not completed an
analysis of the effect that this 6.8 ns period of bus contention has on the
design. An Application Note from
Cypress Semiconductor titled NoBL
SRAM and Bus Contention further explains this bus contention issue.
Physical Dimensions
The footprint of the eZ80F91 Module PCB is 63.5 mm x 78.7 mm. With
an RJ-45 Ethernet connector, the overall height is 25 mm. See
Figure 12 .