Zilog EZ80F91 - Manual (Page 56)

eZ80F91 Development Kit
User Manual
UM014220-0508 eZ80F91 Module
51
//Init_IRDA
// Make sure to first set PD2 as a port bit, an output and set it Low.
PD_ALT1 &= 0xFC; // PD0 = uart0tx, PD1 = uart0_rx
PD_ALT2 |= 0x03; // Enable alternate function
UART_LCTL0= 0x80; // Select dlab to access baud rate generator
BRG_DLRL0=0x2F; // Baud rate Masterclock/(16*baudrate)
BRG_DLRH0=0x00; // High byte of baud rate
UART_LCTL0=0x00; // Disable dlab
UART_FCTL0=0xC7; // Clear tx fifo, enable fifo
UART_LCTL0=0x03; // 8bit, N, 1 stop
IR_CTL = 0x03; // enable IRDA Encode/decode and Receive
// enable bit.
//IRDA_Xmit
IR_CTL = 0x01; //Disable receive
Putchar(0xb0); //Output a byte to the uart0 port.
Flash Loader Utility
The Flash Loader utility integrated within ZDS II provides a convenient
way to program on-chip Flash memory. Refer to Zilog Developer Studio
II—eZ80Acclaim!
®
User Manual (UM0144) for more details.
Mounting the Module
The eZ80F91 Module features two 60-pin connectors. However, the
eZ80Acclaim!
®
Development Kit contains 50-pin sockets for this mod-
ule. When mounting the eZ80F91 Module onto the eZ80Acclaim! Devel-
opment Kit, check its orientation to the platform to ensure a correct fit.
Observe the underside of the module to note that pin 60 of the JP2 con-
nector is removed and that its corresponding socket on the eZ80Acclaim!
Development Kit is plugged.
Pin 60 of the eZ80F91 Module’s JP1 connector must align with the pin 50
socket on the eZ80Acclaim! Development Kit’s JP1 connector; pin 60 of
the eZ80F91 Module’s JP2 connector must align with pin 50 of the