Zilog EZ80F91 - Manual (Page 16)

eZ80F91 Development Kit
User Manual
UM014220-0508 eZ80 Development Kit
11
The description of these five signals are provided below.
Enable Flash— When active Low, the EN_Flash input signal enables the
Flash chip on the eZ80F91 Module.
Flash Write Enable— When active Low, the FlashWE input signal
enables write operations on the Flash boot block of the eZ80F91 Module.
Disable IrDA— When the DIS_IrDA input signal is pulled Low, the IrDA
transceiver, located on the eZ80F91 Module, is disabled. As a result,
UART0 can be used with the RS-232 or the RS-485 interfaces on the
eZ80Acclaim!
®
Development Kit.
F91_WE— When the F91_WE signal is active Low, internal Flash on the
eZ80F91 Module is enabled for writing. This signal is inverted from the
WP signal of on the eZ80F91 Module.
RTC_V
DD
— RTC_V
DD
is a test point for the Real Time Clock power sup-
ply.
Peripheral Bus Connector
Figure 6 displays the pin layout of the Peripheral Bus Connector in the
50-pin header, located at position JP1 on the eZ80Acclaim! Development
Kit.
Table 3 on page 13 lists the pins and their functions.