Zilog S3F8S19 - Manual (Page 23)

UM026801-0914 20
S3F8S19 Development Kit
User Manual
Figure 21. S3F8S19 Development Board Schematic Diagram, #2 of 2
UART CONNECTION
UART CONFIGURATION:
S3F8S19 UART1 R41 R39 (DEFAULT)
Z8F6481 UART0 R40 R38
UART
PA5_TXD0
PA4_RXD0
VCC_T
Z_DBG
Z_RST
Z_RST
Z_DBG
Z_RST
PD5_TXD1
XOUT XIN
XOUT
XIN
PD4_RXD1
RxD
S3_RXD1
PA4_RXD0
S3_TXD1
PA5_TXD0
PA6_SCL
PC4_MOSI
PC5_SCK0
PA7_SDA
PC2_SS-
VCC_5V
VCC_T
VCC_T
VCC_T
VCC_5v
S3_TXD1
S3_RXD1
S3_RXD0
S3_TXD0
S3_SDA
S3_SCK
S3_MOSI
S3_SCL
S3_SS-
S3_MISO
R38 100 ohm
R17
19.6K
R18
10K
R41 0 ohm
R14
470
Y3
24.000MHZ
R34
3.3K
D7
1N4448W
R19
10K
U3
MIC5318
GND
2
EN
1
IN
3
ADJ
5
OUT
4
BYP
6
Center Pad
7
R20
27
J14
1
C12
0.01uF
C13
4.7uF
J15
1
R21
27
L1
FERRITE BEAD
C11
0.01uF
R39 100 ohm
C14
0.1uF
J12
1
C9
4.7uF
C15
12pF
P1
USB, mini B
VBUS
1
DM
2
DP
3
ID
4
GND
5
SH1
6
SH2
7
SH3
8
SH4
9
h1
10
h2
11
R40 0 ohm
J16
HDR/PIN 2x3
1 2
3 4
5 6
C16
12pF
C8
1uF
C5
4.7uF
C10
0.1uF
R35
4.7K
R16
20K
1
3
2
J11
1
D5
GREEN
2 1
C7
1uF
Z8F6481AN
U4
PA2
/DE0
/C
LK
2 IN
/X
2I
N
1
PA3
/CT
S0
-/X2
O
UT
2
PE
3 /T
4C
H
A/
ESO
U
T0
3
PD6
/D
E1
4
PA4
/RXD0
/MO
SI0
5
PA5
/TXD
0/
S C K 0
6
P D5
/T
X D1
7
PA
6 /T
1I
N
/T
1O
U T-
/S
CL
8
PC4
/MO
SI0
/T0
IN/T0
O
U
T-/SCL
/D
E0
9
P C5
/SC
K0
/T0
OUT
/S
DA/CTS
0-
10
PA
7 /T
1O
U
T /S
DA
1 1
PD4/RXD1
12 PC6/T2IN/T2OUT-/SCKOUT/ESOUT0
13 PC7/T2OUT/CTS1-/ESOUT1
14 VDD
15 PD0/RESET-
16 DBG
17 PD3/C1OUT/AMPBOUT/ANA8
18 VSS
19
PC0/ANA4/VBIAS/C0INP
21 PC1/MISO0/ANA5/C0INN
22
PC2
/AN
A3
/SS0
-
23
PC
3/
M
IS
O0
/A
NA
11
/DAC
24
PD2
/C1
IN
P/AM
PBI
N
P/
A
NA6
2 5
P D1
/C1
INN
/AM
PB
INN/ANA
7
26
PB0
/AN
A0
/AM
PAO
UT
27
PB
1 /A
NA1
/AM
PAINN
2 8
PB
2 /A
NA2
/AM
PAINP
2 9
PB4
/VR
EF+
30
PB3
/VRE
F-
31
PE5
/T4
CHC/
ESO
UT
2
32
PE6
/T4
CHD
/ESO
UT
3
3 3
PE2/T4IN
34
VCORE
35
AVDD
36
VDD
37
PA0/T0IN/T0OUT-/CLKIN/XIN
38
PA1/T0OUT/XOUT
39
VSS
40
AVSS
41
PD7/C0OUT
42
PE1/DM/T0OUT
43
PE0/DP/T0IN/T0OUT-
44
PE4/T4CHB/ESOUT1
20
J20
1
2
3
4
5
6
R15
16.5K
R36 3.3K
C6
0.1uF
R33 4.7K