Altera Stratix III - Manual (Page 23)

Chapter 5: Power Measurement 5–5
Changing the Design Example
© August 2008 Altera Corporation Stratix III Development Kit User Guide
then
where
V
SUPPLY
is 1.1 V for the FPGA core and 2.5 V for FPGA I/O.
Voltage measurements on the DMM should increase as frequency and resource
utilization increases according to
Table 5–2 and Table 5–3 on page 5–2 .
Changing the Design Example
The development kit includes source code for the Stratix III power design example so
you can use it as a starting point for your own measurements.
The design example uses 20 stamp.v modules, each with 8 outputs, for a total of
160 output pins. It assigns the pins selected as outputs to the HSMC connectors J8 and
J18.
To change the number of outputs, modify the design example and assign the pins
appropriately.
1
Power should track linearly with frequency and percentage resources. If you observe
superlinear power measurements, some temperature issue may be the cause.
Equation 5–1.
P VI V
SUPPLY
I
SENSE
×
V
SUPPLY
V
SENSE
×
R
SENSE
--------------------------------------------- = = =