Altera First-In-First-Out Partitioner - Manual (Page 7)

Altera Corporation 5
Getting Started
Introduction The FIFO Partitioner is a tool for mapping multiple FIFOs into a single
physical memory block. The ability to partition M-RAM blocks into
multiple FIFOs greatly enhances the utility of the TriMatrix memory
architecture. The FIFO Partitioner automatically generates the logic
necessary to time-domain-multiplex Stratix M-RAM blocks between
multiple user-specified FIFOs. Use the FIFO Partitioner for FIFO functions
that can't be fit efficiently into available M512 or M4K blocks.
Figure 1. User's View of a FIFO Partitioner Function Note (1)
Notes:
(1) Total number of FIFOs, n, should not exceed 10 for most designs. Up to 256 FIFOs
are possible for designs with moderate performance requirements.
M-RAM Block
FIFO 0
FIFO 1
FIFO n 1
Read-Side
FIFO Ports Write-Side
FIFO Ports