Altera Cyclone III LS FPGA - Manual (Page 31)

Chapter 6: Board Test System 6–13
The Power Monitor
© October 2009 Altera Corporation Cyclone III LS FPGA Development Kit User Guide
 HSMA x41 Single Ended Loopback
 HSMB x41 Single Ended Loopback
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
 PRBS —Selects pseudo-random bit sequences.
 Memory —Selects a generic data pattern stored in the on chip memory of the
Cyclone III LS device. This feature is not currently implemented.
 Math —Selects data generated from a simple math function within the FPGA
fabric. This feature is not currently implemented.
Error Control
These controls track transaction errors detected during analysis.
 Detected Errors —Displays the number of transaction errors detected in the
hardware.
 Inserted Errors —Displays the number of errors inserted into the transaction
stream.
 Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
 Clear —Resets the Detected Errors and Inserted Errors counters to zeros.
Start
This control initiates HSMC transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
 TX and RX performance bars—Show the percentage of maximum data rate that
the requested transactions are able to achieve.
 Tx(MBytes/s) and Rx(MBytes/s)—Show the number of bytes of data analyzed per
second.
The Power Monitor
The Power Monitor measures and reports current power information for the board. To
start the application, click Power Monitor in the Board Test System application.