Altera Cyclone III LS FPGA - Manual (Page 28)

6–10 Chapter 6: Board Test System
Using the Board Test System
Cyclone III LS FPGA Development Kit User Guide © October 2009 Altera Corporation
The following sections describe the controls on the DDR2 tab.
Port
This control directs communication to one of two DDR2 memory ports on your board.
Start
This control initiates DDR2 port transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
 Write , Read, and Total performance bars—Show the percentage of maximum data
rate that the requested transactions are able to achieve.
Figure 6–5. The DDR2 Tab