Altera Cyclone III LS FPGA - Manual (Page 29)

Chapter 6: Board Test System 6–11
Using the Board Test System
© October 2009 Altera Corporation Cyclone III LS FPGA Development Kit User Guide
 Write(MBytes/s) , Read(MBytes/s), and Total(MBytes/s)—Show the number of
bytes of data analyzed per second. Each data bus is 16 bits wide and the frequency
is 167 MHz double data rate (334 Mbps per pin), equating to a theoretical
maximum bandwidth of 668 MBps.
Error Control
These controls track transaction errors detected during analysis:
 Detected Errors —Displays the number of transaction errors detected in the
hardware.
 Inserted Errors —Displays the number of errors inserted into the transaction
stream.
 Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
 Clear —Resets the Detected Errors and Inserted Errors counters to zeros.
Number of addresses to write / read
This control determines the number of addresses to use in each iteration of reads and
writes. Valid values range from 2 to 8,191.
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
 PRBS —Selects pseudo-random bit sequences.
 Memory —Selects a generic data pattern stored in the on chip memory of the
Cyclone III LS device.
 Math —Selects data generated from a simple math function within the FPGA
fabric.
Read/Write control
This control specifies the type of transactions to analyze. The following transaction
types are available for analysis:
 Write/Read —Selects read and write transactions for analysis.
 Read Only —Selects read transactions for analysis.
 Write Only —Selects write transactions for analysis.
The HSMC Tab
The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B
ports.
Figure 6–6 shows the HSMC tab.