Board components, Board overview, Chapter 3. board components – Altera MAX 10 FPGA User Manual
Page 13: Board overview –1
October 2014
Altera Corporation
MAX 10 FPGA (10M08S, 144-EQFP) Evaluation Kit
User Guide
3. Board Components
This chapter introduces all the important components on the evaluation kit.
Figure 3–1
illustrates major component locations and
Table 3–1
provides a brief
description of all features of the board.
Board Overview
This section provides an overview of the evaluation kit, including an annotated board
image and component descriptions.
Table 3–1
describes the components and lists their corresponding board references.
Figure 3–1. Overview of the MAX 10 FPGA Evaluation Kit Features
JTAG
Header
(J10)
Arduino
Connector
2x20 GPIO
Through-Hole Vias (J9)
Arduino
Connector
Arduino
Connector
Jumper
(J6)
Jumper
(J7)
2x20 GPIO
Through-Hole Vias (J8)
SW1
SW3
LEDs
USB
Connector
(J1)
SW2
Prototype
Area
MAX 10
FPGA (U2)
Arduino
Connector
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)