ADLINK PCI-9810 - Manual (Page 49)

Operation Theory 37
NOTE The clock divider must be an even number (2, 4, 6, 8,
10… 65534), with the minimum divider value being 2. Re-
fer to section 6.2 to set the clock source and frequency di-
vider.
The first AD sample takes several clocks to convert be-
cause of the ADC’s pipelined architecture. Therefore, the
external clock must be continuous for correct AD opera-
tion.
X Multiple cards operation
When multiple cards are installed in a single system, 4-chan-
nels on one card can achieve simultaneous conversion since
they have the same internal clock source. However, the chan-
nels between two cards cannot be synchronized because the
clock sources on different cards come from different sources.
Even when the same external clock source is applied to all
cards, the A/D conversion time is still possibly asynchronous
because an onboard clock divider (divisible by 2) is used.
Therefore, when the same external clock source is applied to
multiple cards, the time difference of the sampling clocks
between two cards will be half of the sampling clock period.
The A/D clock cannot synchronize multiple cards.