ADLINK PXIe-9852 User Manual
Page 40

30
Operations
Trigger Mode” on page 22. and “Middle Trigger Mode” on
page 23.). This slave device should set one PXI_BUS pin, not
used to transmit and receive SSI_TRIG1, to output to transmit its
pre_data_ready signal to master device. If any other slave device
is in pre-trig/mid-trig mode, it should set another PXI_BUS pin to
send its pre_data_ready signal. In this scenario, a single line on
PXI_BUS is used to transmit trigger signals from master to slave,
while other specified lines are used to transmit pre_data_ready
signals from slave devices in pre-trig/mid-trig mode to a master
device. From the master device, one pin is assigned as output to
transmit trigger signal. The trigger signal won’t be sent out until all
slaves’ pre_data_ready is received by the master device.
- USB-1901 (84 pages)
- USB-1210 (54 pages)
- USB-2401 (60 pages)
- USB-7230 (50 pages)
- USB-2405 (56 pages)
- DAQe-2010 (92 pages)
- DAQe-2204 (100 pages)
- DAQe-2213 (94 pages)
- DAQe-2501 (74 pages)
- PXI-2010 (84 pages)
- PXI-2020 (60 pages)
- PXI-2501 (62 pages)
- cPCI-9116 (98 pages)
- ACL-8112 Series (93 pages)
- ACL-8112 Series (94 pages)
- ACL-8112 Series (92 pages)
- ACL-8216 (75 pages)
- ACL-8111 (61 pages)
- PCM-9112+ (94 pages)
- PCM-9112+ (10 pages)
- cPCI-6216V (47 pages)
- ACL-6126 (28 pages)
- ACL-6128A (40 pages)
- PCM-6308V+ (4 pages)
- PCM-6308V+ (52 pages)
- PCI-7444 (82 pages)
- PCI-7434 (48 pages)
- PCI-7234 (56 pages)
- PCI-7260 (66 pages)
- PCI-7258 (38 pages)
- PCI-7256 (48 pages)
- PCI-7250 (48 pages)
- LPCI-7250 (48 pages)
- PCI-7396 (65 pages)
- PCI-7296 (59 pages)
- PCI-8554 (67 pages)
- PCIe-7360 (94 pages)
- PCIe-7350 (86 pages)
- PCIe-7300A (114 pages)
- PCIe-7200 (51 pages)
- PCI-7300A (112 pages)
- PCI-7300A (83 pages)
- PCI-7200 (96 pages)
- cPCI-7300 (82 pages)
- cPCI-7300 (83 pages)