ADLINK PXIe-9852 - Manual (Page 30)

20 Operations
Triggering occurs when a rising edge or falling edge is detected
at PXI STAR, with trigger polarity configurable by software. The
minimum pulse width requirement of this digital trigger signal is 20
ns.
3.3.4 PXIe_DSTARB Trigger
The PXIe_DSTARB signal, a differential signal transmitted via the
PXI Express Chassis backplane, distributes high-speed, high-
quality trigger signals. When PXIe_DSTARB is selected as the
trigger source, the PXIe-9852 accepts a fast-switching LVDS digi-
tal signal as a trigger signal. Triggering occurs when a rising edge
or falling edge is detected at PXIe_DSTARB, with trigger polarity
configurable by software, with minimum pulse width requirement
of 20 ns.
3.3.5 PXI Trigger Bus
The PXIe-9852 utilizes PXI Trigger Bus Numbers 0 through 7 to
act as a System Synchronization Interface (SSI). With the inter-
connected bus provided by PXI Trigger Bus, multiple modules are
easily synched. When configured as input, the PXIe-9852
serves as a slave module and can accept trigger signals from one
of buses 0 through 7. When configured as output, the PXIe-9852
serves as a master module and can output trigger signals to the
PXI Trigger Bus Numbers 0 through 7.
3.3.6 Analog Trigger
An analog trigger is generated when AI input signal level is
detected at the SMA connector CH0, CH1 (selected by software).
The trigger level is also selected by software.