ADLINK PCI-8554 - Manual (Page 32)

22 • Getting Started
DB_CLK
input
signal
output
signal
glitch is
eliminated
Figure 17: Basic Timing of the debounce system
2.14 Interrupt System
The cPCI/PCI-8554/R‘s interrupt system is a powerful and flexible system,
which is suitable for many applications. The system is a Dual Interrupt
System. Dual Interrupt means the hardware can generate two interrupt
request signals simultaneously and the software is able to respond and
invoke the ISR. Note that dual interrupt do not mean the card will occupy
two IRQ levels. These two interrupt request signals INT1 and INT2 are
generated by the external interrupt signal EXTINT and the timer/counter
12 output. Figure 18 shows the structure of interrupt system.
COUT12
Counter #12
8254 Chip #4
Counter #11
8254 Chip #4
'H'
'H'
8MHz
IRQ
Flip-
Flops
IRQ
Flip-
Flops
PCI
Controller
INT #A
INT1
INT2
Clear by "8554_CLR_IRQ1"
Clear by "8554_CLR_IRQ2"
EXTINT
E_INT
debounce
system
DB_CLK
JP11
Figure 18: Dual Interrupt System of cPCI/PCI-8554/R