ADLINK cPCI-9116 - Manual (Page 42)

32
• Registers
SCTC_en (bit11): Trigger Complete Interrupt Enable Control
1: Enable
0: Disable
Hfull_en (bit10): A/D FIFO Half Full Interrupt Enable Control
1: Enable
0: Disable
DTrg_en (bit9): External Digital Trigger Interrupt Enable Control
1: Enable
0: Disable
EOC_en (bit8): End of conversion Interrupt Enable Control
1: Enable
0: Disable
Clr_Timer (bit4): write 1 to clear the GPTC Interrupt status
1: clear interrupt from the GPTC
0: no effect
Clr_SCTC (bit3): write 1 to clear the SCTC Interrupt
1: clear the interrupt on terminal count of the Scan counter
0: no effect
Clr_HFull (bit2): write 1 to clear the data FIFO half full interrupt
1: clear the interrupt on the data FIFO half full status
0: no effect
Clr_DTrg (bit1): write 1 to clear the Digital Trigger Interrupt
1: clear the interrupt when trigger happens
0: no effect
Clr_EOC (bit0): write 1 to clear the End of Conversion Interrupt
1: clear the interrupt when EOC
0: no effect