ADLINK cPCI-9116 - Manual (Page 33)

Registers
• 23
Counter en (bit7): GPTC0 count enable
1: enable GPTC0
0: disable GPTC0
UpDown (bit6): GPTC0’s up/down pin software control
1: Up counter
0: Down counter
UpDown src(bit5): GPTC0’s up/down pin selection bit
1: External input (Pin 98)
0: Software Control
Gate_src (bit4): GPTC0’s gate source
1: External Input (Pin 97)
0: gate controlled by setting the enable (bit7)
Clk_src (bit3): GPTC0’s clock source
1: External Input (Pin 96)
0: Internal Timebase
MODE1~MODE0 (bit1 ~ bit0): GPTC0’s Mode selection
MODE1 MODE0 Description
0 0 General Counter
0 1 Pulse Generation
1 0 X
1 1 X
Table 6. GPTC0’s Mode selection