Truth table – Cypress CY7C1345G User Manual
Page 8
CY7C1345G
Document Number: 38-05517 Rev. *E
Page 8 of 20
Truth Table
The truth table for CY7C1345G follows.
Cycle Description
Address
Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC ADV WRITE
OE
CLK
DQ
Deselected Cycle, Power
down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselected Cycle, Power
down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle, Power
down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle, Power
down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselected Cycle, Power
down
None
X
X
X
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
1. X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals (BW
A
, BW
B
, BW
C
, BW
D
) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW
A
,
BW
B
, BW
C
, BW
D
), BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[A: D]
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).