Cypress CY7C1345G - Manual (Page 20)

Document Number: 38-05517 Rev. *E Revised July 15, 2007 Page 20 of 20
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CY7C1345G
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Document History Page
Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM
Document Number: 38-05517
REV. ECN NO. Issue Date
Orig. of
Change
Description of Change
** 224365 See ECN RKF New datasheet
*A 278513 See ECN VBL Deleted 66 MHz
Changed TQFP package to Pb-free TQFP in Ordering Information section
Added BG Pb-free package
*B 333626 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
OL,
V
OH
test conditions
Replaced ‘Snooze’ with ‘Sleep’
Removed 117 MHz speed bin
Replaced TBDs for Θ
JA
and Θ
JC
to their respective values on the Thermal Resis-
tance table
Removed comment on the availability of BG Pb-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C 418633 See ECN RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V
IH
< V
DD
to V
IH
< V
DD.
Modified test condition from V
DDQ
< V
DD
to V
DDQ
< V
DD
Modified Input Load to Input Leakage Current except ZZ and MODE in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Updated the Ordering Information table.
*E 1274724 See ECN VKN Corrected Write Cycle timing waveform