Cypress CY7C1345G - Manual (Page 14)

CY7C1345G
Document Number: 38-05517 Rev. *E Page 14 of 20
Figure 2 shows the write cycle timing. [15, 16]
Figure 2. Write Cycle Timing
Timing Diagrams
(continued)
t CYC
t
CL
CLK
tADH tADS
ADDRESS
t
CH
tAH tAS
A1
tCEH tCES
High-Z
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3)
A2 A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH tADS
tADH tADS
t
OEHZ
tADVH tADVS
tWEH tWES
t
DH
t
DS
t
WEH
t
WES
Byte write signals are ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
ADSP
ADSC
BWE,
BW [A:B]
GW
CE
ADV
OE
Data in (D)
Data Out (Q)
Note:
16. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
x
LOW.