Cypress CY7C1345G - Manual (Page 5)

CY7C1345G
Document Number: 38-05517 Rev. *E Page 5 of 20
Pin Definitions
Name IO Description
A0, A1, A Input
Synchronous
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed
the two-bit counter.
BW
A,
BW
B
BW
C
, BW
D
Input
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW Input
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
BWE Input
Synchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
LOW to conduct a byte write.
CLK Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
1
Input
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
CE
2
Input
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is
loaded.
CE
3
Input
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is
loaded.
OE Input
Asynchronous
Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When
LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV Input
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
ADSP Input
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
1
is deasserted HIGH.
ADSC Input
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ZZ Input
Asynchronous
ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.
DQs
DQP
A,
DQP
B
DQP
C,
DQP
D
IO
Synchronous
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and
DQP
[A:D]
are placed in a tri-state condition.
V
DD
Power Supply Power supply inputs to the core of the device.
V
SS
Ground Ground for the core of the device.
V
DDQ
IO Power
Supply
Power supply for the IO circuitry.
V
SSQ
IO Ground Ground for the IO circuitry.