Cypress Perform CY7C136A - Manual (Page 9)

CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Document #: 38-06031 Rev. *E Page 9 of 15
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
[12, 21]
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
Switching Waveforms
(continued)
t
AW
t
WC
t
SCE
t
SA t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D
OUT
DATA
IN
t
LZWE
DATA VALID
ADDRESS MATCH
t
PS
CE
L
Valid First:
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
BUSY
L
CE
R
CE
L
ADDRESS
L,R
BUSY
R
CE
L
CE
R
ADDRESS
L,R
CE
R
Valid First:
Note
21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
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