Digilent MX3cK - Manual (Page 10)

Cerebot MX3cK Reference Manual
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PIC32 Peripheral Devices
The following describes the peripheral devices
available in the PIC32MX460F512L
microcontroller and how they are accessed on
the Cerebot MX4cK board.
CPU Clock Source
The PIC32 microcontroller supports numerous
clock source options for the main processor
operating clock. The Cerebot MX3cK uses an
8Mhz external crystal for use with the XT
oscillator option. Oscillator options are
selected via the configuration settings specified
using the #pragma config statement. Use
#pragma config POSCMOD=XT
to select the
XT option.
Using the internal system clock phase-locked
loop (PLL), it is possible to select numerous
multiples or divisions of the 8Mhz oscillator to
produce CPU operating frequencies up to
80Mhz. The clock circuit PLL provides an input
divider, multiplier, and output divider. The
external clock frequency (8Mhz) is first divided
by the input divider value selected. This is
multiplied by the selected multiplier value and
then finally divided by the selected output
divider. The result is the system clock,
SYSCLK, frequency. The SYSCLK frequency
is used by the CPU, DMA controller, interrupt
controller and pre-fetch cache.
The values controlling the operating frequency
are specified using the PIC32MX320
configuration variables. These are set using
the #pragma config statement. Use
#pragma config FPLLIDIV
to set the input
divider, #pragma config FPLLMUL to set
the multiplication factor and #pragma config
FPLLODIV
to set the output divider. Refer to
the PIC32MX3XX/4XX Family Data Sheet and
the PIC32MX Family Reference Manual,
Section 6. Oscillators, for information on how
to choose the correct values, as not all
combinations of multiplication and division
factors will work.
In addition to configuring the SYSCLK
frequency, the peripheral bus clock, PBCLK,
frequency is also configurable. The peripheral
bus clock is used for most peripheral devices,
and in particular is the clock used by the
timers, and serial controllers (UART, SPI, I2C).
The PBLCK frequency is a division of the
SYSCLK frequency selected using #pragma
config FPBDIV
. The PBCLK divider can be
set to divide by 1, 2, 4, or 8.
The following example will set up the Cerebot
MX3cK for operation with a SYSCLK frequency
of 80Mhz and a PBCLK frequency of 10Mhz:
#pragma config FNOSC = PRIPLL
#pragma config POSCMOD = XT
#pragma config FPLLIDIV = DIV_2
#pragma config FPLLMUL = MUL_20
#pragma config FPLLODIV = DIV_1
#pragma config FPBDIV = DIV_8
Documentation for the available PIC32
configuration variables can be found in the
PIC32MX Configuration Settings guide. This is
found using the “Help.Topics…” in the MPLAB
IDE. Refer to Appendix E for an example of
setting the configuration variables.
When using the Cerebot MX3cK with the
chipKIT MPIDE software, the clock source is
automatically set by the boot loader and no
action is required.
UART Interface
The PIC32MX320 microcontroller provides two
UART interfaces, UART1 and UART2. The
UARTs can provide either a 2-wire or a 4-wire
asynchronous serial interface. The 2-wire
interface provides receive (RX) and transmit
(TX) pins. The 4-wire interface includes
request-to-send (RTS) and clear-to-send
(CTS) in addition to receive and transmit.
UART1 can be accessed from Pmod connector
JB and UART2 can be accessed from Pmod
connector JC using the following pins: