Digilent 210-251P-BOARD - Manual (Page 7)

JTAG-SMT2 Reference Manual
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Page 7 of 11
Example 2: Interfacing a Zynq-7000 that uses different voltages for VCCO_0 and VCCO_MIO1
Figure 10 demonstrates how to connect the JTAG-SMT2 to Xilinx’s Zynq-7000 silicon when different voltages
supply the VCCO_0 (Programmable Logic Bank 0 Power Supply) and VCCO_MIO1 (Processor MIO Bank 1 Power
Supply). If the Zynq’s JTAG pins are operating at a different voltage than the PS_SRST_B, it requires an external
buffer to adjust the level of the GPIO2 signal. The example in Fig. 10 demonstrates the use of an open drain buffer
to allow for the possibility of adding a reset button.
VCCO_0
VCCO_MIO1
PS_SRST_B
ZYNQ-
7000
TDO
TMS
TDI
TCK
GND
VDD
VREF
TDO
JTAG-
SMT2
GND
TMS
TDI
TCK
GPIO0
GPIO1
GPIO2
VCCO_0
VCCO_MIO1
3.3V
VCCO_0
VCCO_MIO1
10K
Optional Reset
Button
Figure 10. Use of an open drain buffer.