Cypress CY7C1338G - Manual (Page 11)

CY7C1338G
Document #: 38-05521 Rev. *D Page 11 of 17
Timing Diagrams
Read Cycle Timing [17]
Note:
17. On this diagram, when CE is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
tCYC
t
CL
CLK
tADH tADS
ADDRESS
t
CH
tAH tAS
A1
tCEH tCES
Data Out (Q) High-Z
tCLZ
tDOH
tCDV
tOEHZ
tCDV
Single READ BURST
READ
tOEV tOELZ
tCHZ
Burst wraps around
to its initial state
t
ADVH
t
ADVS
t
WEH
t
WES
tADH tADS
Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3)
A2
ADV suspends burst.
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW
[A:D]
CE
ADV
OE