Kontron CP371 - Manual (Page 53)

CP371 Configuration
ID 23762, Rev. 02 © 2002 PEP Modular Computers GmbH Page 4 - 9
4.3.3 Programming the Board Capability ROM
Besides correction data for gain and offset errors other board specific capabilities can be stored
in this dedicated onboard ROM. The purpose is that software will be able to configure itself,
according to the hardware version (i.e. type, number of channels, insertion of components, in-
put circuit, etc.).
The Board Capability ROM is implemented using a 4 KBit serial EEPROM of the type 93LC66
from Microchip.
The serial interface of the device has been realized in hardware resulting in a very simple reg-
ister based programming interface with command, control, and data registers. All protocol and
serial timing specifications are resolved by hardware.
Programming of the Board Capability ROM is undertaken as follows: The control word is written
into the ROM Control Register including command opcode and internal address. Then optional
data (in case of Write action) is written into the ROM Data Register. Command execution is
started by setting the Startbit in the ROM Command Register. Then Ready/Busy must be polled
in the ROM Status Register. After reaching Ready status, the next command can be set up and
data (in case of Read action) can be fetched from the ROM Data Register.
Note: The Startbit will automatically be reset as soon as an action is completed.
Note: The commands READ, EWEN (write enable) and WRITE are sufficient for all
purposes.
Table 4-5: ROM Command Register Bit Map
BITS TYPE DEFAULT FUNCTION
31 R/W 0 Startbit
30 - 0 R/W 00 reserved
Table 4-6: ROM Control Register Bit Map
BITS TYPE DEFAULT FUNCTION
31 - 18 R/W 0 reserved
17 - 16 R/W 00 Opcode
15 - 9 R/W 00 reserved
8 - 0 R/W 00 internal address (A8..A0)