Kontron CP382 - Manual (Page 48)

Configuration CP382
Page 4 - 6 © 2002 PEP Modular Computers GmbH ID 24208, Rev. 01
4.3 Programming Interface
4.3.1 Access Control Logic (Address Decoder)
All the resources of the CP382 are mapped within the 64 kB PCI memory address space which
itself is set in the PCI configuration register BAR0. The port size of all local or backend registers
is 32-bit by default. The address map of the registers is as follows.
Table 4-1: Backend Register Address Map
Base Address Size Function
bar0 + 0x0000 4 K Common Board Registers
0x0400 32 bit g_irq General Interrupt Enable Register
0x0800 32 bit hsr Hardware Status Register
0x0804 32 bit i_pen General Interrupt Pending Register
0x0c00 32 bit hdr Hardware Debug Register
bar0 + 0x1000 4 K Capability ROM, serial EEPROM
0x1000 32 bit r_cmd Command Register
0x1400 32 bit r_ctl Control Register
0x1800 32 bit r_sta Status Register
0x1c00 32 bit r_dat Data Register
bar0 + 0x2000 4 K DigOUT Cluster A
0x2400 32 bit o_ctl_a Output Control Register
0x2800 32 bit o_sta_a Output Status Register
0x2c00 32 bit o_dat_a Output Data Register
bar0 + 0x3000 4 K DigOUT Cluster B
0x3400 32 bit o_ctl_b Output Control Register
0x3800 32 bit o_sta_b Output Status Register
0x3c00 32 bit o_dat_b Output Data Register
bar0 + 0x4000 4 K DigOUT Cluster C
0x4400 32 bit o_ctl_c Output Control Register
0x4800 32 bit o_sta_c Output Status Register
0x4c00 32 bit o_dat_c Output Data Register
bar0 + 0x5000 - 0xffff 44 K Reserved