Synplify Pro always performs optimization on the redundant or feed-through nets. At times,
the user may want to keep these nets. In order for these nets not to get optimized away
(removed), you will have to do the following:

wire net1 /* synthesis syn_keep = 1 */ ;
wire net2 ;
assign net2 = net1 ;

In this above example, the synthesis tool won’t optimize away (remove) the logic. Instead, it
will infer a buffer between the two wire statements. If it is not specified, the user may not see
the buffer insertion by the tool.

The same is true for sequential logic. If you don’t not want the sequential element optimized
away (removed), the following synthesis directive to be added:

reg net_reg1 /* synthesis syn_preserve = 1 */ ;
always @ (posedge clk)
begin

net_reg1 <= some_net

;

end