Achronix Synthesis User Manual
Page 5
UG018, April 15, 2013
5
Select or click on the “New Project” button, then the following window will appear
(shown in Figure 4):
Figure 4 – Properly select the Project database for the synthesis.
After selecting and saving the project file inside the desired directory path, you will have to
add the source RTL files. There are two ways to add the source RTL files. One is using the
“Add File” option from the Left menu bar and the other one is to ‘right click’ on the project
file and select “Add Source File”. Selecting the source will direct the user to a dialog box of
RTL files. Below is an example of the dialog box:
Figure 5 – Add the source file under the user’s project directory
From this dialog box “Select Files to Add to Project” choose your RTL files and then click
“Add” followed by “OK”. The Verilog/VHDL file(s) will now be added to the project for
synthesis.