Achronix Synthesis - Manual (Page 15)

UG018, April 15, 2013 15
Example Synplify-Pro Project File
#-- Synopsys, Inc.
#-- Version F-2011.09X Beta
#-- Project file /home/testing_HD.prj
#project files
add_file -verilog "//Achronix-
linux/libraries/device_models/22i_synplify.v"
add_file -vhdl -lib work " package1.vhd"
add_file -vhdl -lib work "top_level.vhd"
#implementation: "rev_1_HD"
impl -add rev_1_HD -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path /Achronix-linux/libraries/}
#device options
set_option -technology AchronixSpeedster22iHD
set_option -part ACX22iHD1000
set_option -package FBGA2280
set_option -speed_grade Std
set_option -part_companion ""
#compilation/mapping options
set_option -top_module ""
# mapper_options
set_option -frequency
set_option -write_verilog 0
set_option -write_vhdl 0
# Achronix Speedster22iHD
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -retime_registers_forward 0
set_option -time_borrow 0
set_option -pipe 1
set_option -retiming 1
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1