Achronix Synthesis - Manual (Page 10)

10 UG018, April 15, 2013
honored:

Top-level output ports

Input pins of instantiated gates

Pins of inferred instances
-freq Defines the frequency of the clock in MHz. The user can specify
either this or -period, but not both
-period This parameter allows the user to specify the period of the clock
in nanoseconds. The user can specify either this or -freq, but
not both.
-clockgroup This parameter allows the user to specify clock relationships.
The user assigns related (synchronized) clocks to the same clock
group and unrelated clocks in different groups. The synthesis
tool calculates the relationship between clocks in the same clock
group, and analyzes all paths between them. Paths between
clocks in different groups are ignored (false paths). An example
usage with this parameter is provided later in this document
for more information.
Below are examples of clock-constraint commands for a multiple clock domain design:
define_clock {n:spi_refclk} -name {n:spi_refclk} -freq 400 -clockgroup default_clkgroup_0
define_clock {n:rx_sclk} -name {n:rx_sclk} -freq 100 -clockgroup default_clkgroup_0
define_clock {p:spi_tx_sclk[0]} -name {p:spi_tx_sclk[0]} -freq 100 -clockgroup default_clkgroup_1
define_clock {p:spi_tx_sclk[1]} -name {p:spi_tx_sclk[1]} -freq 100 -clockgroup default_clkgroup_2
define_clock {p:spi_tx_sclk[2]} -name {p:spi_tx_sclk[2]} -freq 100 -clockgroup default_clkgroup_3
define_clock {p:spi_tx_sclk[3]} -name {p:spi_tx_sclk[3]} -freq 100 -clockgroup default_clkgroup_4
define_clock {p:spi_tx_sclk[4]} -name {p:spi_tx_sclk[4]} -freq 100 -clockgroup default_clkgroup_5
define_clock {p:spi_tx_sclk[5]} -name {p:spi_tx_sclk[5]} -freq 100 -clockgroup default_clkgroup_6
Memories
Memories can be instantiated in the RTL, or inferred by the Synthesis tool
Memory instantiation or Memory Insertion by the synthesis tool. If user wants to instantiate
memory inside the RTL code, it is totally technology dependent.
Block RAM (BRAM)
The user can also specify the memory type inside the RTL code in order to have it inferred by
the synthesis tool. Following is the statement to infer memory:
For Verilog:
reg [4:0] mem_array [0:255] /* synthesis syn_ramstyle = "block_ram,no_rw_check" */;
For VHDL:
type array512x36 is array(0 to 511) of std_logic_vector (DW-1 downto 0);
signal mem : array512x36;
attribute syn_ramstyle : string ;
attribute syn_ramstyle of mem : signal is "block_ram, no_rw_check";