Achronix Synthesis - Manual (Page 12)

12 UG018, April 15, 2013
Local Ram (LRAM)
Distributed RAM or LRAM inferring or instantiation: Synplify-Pro is able to infer (or
instantiate) LRAMs. With the current Synplify release, there must be a register at the output
of the read port or the read address has to be registered to infer the LRAM. Inferred
asynchronous reads from the LRAM are not yet supported. Also, with the current Synplify
release, initializing the LRAM is not yet supported. Both the asynchronous read and the
LRAM initialization are planned for the next release (when it is available). Note the LRAM
initialization is required to support ROMs.
For Verilog:
reg [5:0] addr_reg ;
always @ (posedge clk) addr_reg <= addr_ports ;
reg [9:0] mem_array [0:63] /* synthesis syn_ramstyle=”logic_ram”*/;
For VHDL:
type array63x10 is array(0 to 63) of std_logic_vector (9 downto 0);
signal mem_array : array63x10;
attribute syn_ramstyle : string ;
attribute syn_ramstyle of mem_array : signal is "logic_ram";
Finite State Machines
Finite State Machine (FSM) Compiler
The FSM Compiler is an automatic tool for encoding state machines. FSM coding style in the
RTL design will directly impact performance. User should consider this carefully. By default
Synplify-Pro performance as follows:
0-4 states is Binary Encoding
5-40 states is One Hot Encoding
>40 states is Gray Encoding
If the user wants to specify FSMs differently with attributes, here are the steps:
To generate better results for the state machines :
The software uses optimization techniques that are specifically tuned for FSMs such as reach
ability analysis. The FSM Compiler may convert this encoded state machine into a different
encoding style (to improve speed and area utilization) without changing the source. For
example, the user can use the one-hot style to improve results.
To debug the state machines:
State machine description errors result in unreachable states, so if the user has errors, the user
will have fewer states. The user can then check whether the source code describes the state(s)
correctly. The user can also use the FSM Viewer to see a high-level bubble diagrams and
cross-probe from there.
FSM Encoding: For VHDL users
there are two choices to define the encoding via attributes in the RTL code:

Use “syn_encoding” attribute and enable the FSM compiler.

Use “syn_enum_encoding” to define the states (sequential, one-hot, gray, and safe)
and disable the FSM compiler. If the user does not disable the FSM compiler, the
“syn_enum_encoding: values are not implemented. This is because the FSM
compiler, which is a mapper operation, overrides any user attributes for the FSM