Achronix Synthesis - Manual (Page 13)

UG018, April 15, 2013 13
encoding. The FSM compiler can be disabled via the GUI or the from the Synplify
project file with the following syntax:
set_option –symbolic_fsm_compiler 0
The user may also direct the synthesis process to deploy a user-defined FSM
encoding. An example:
VHDL:
attribute syn_enum_encoding of state_type: type is “001 010 101” ;

There is a synthesis attribute to turn on/off FSM extraction. By using this attribute the
user can see how state machines are extracted. Setting attributes in the source code is
shown in the following table
Specify a state machine for extraction and optimization syn_state_machine=1
Prevent state machines from being extracted and optimized syn_state_machine=0
An example for VHDL design:
------ Attribute ----
attribute syn_state_machine : boolean;
attribute syn_state_machine of tx_training_cstate : signal is true;
An example for Verilog design:
If user does not want to optimize the state machine, add the
syn_state_machine directive to the registers in the Verilog code.
Set the value to 0. When synthesized, these registers are not extracted
as state machines.
reg [39:0] curstate /* synthesis syn_state_machine=0 */ ;
For the above 40 states, Synplify Pro performs Gray encoding. If the user wants to do One
Hot Encoding then he will have to do the following:
reg [39:0] state /* synthesis syn_encoding = "onehot" */ ;
Replication of States that have high fan-ins
Large and complex state machines present another unique challenge in state machine design.
Complex state machines can be made to run faster by actually making them larger, that is by
adding more states. This technique can be counter intuitive as the number of levels of logic
between the states and not the number of states typically limits state machine performance.
The performance of a state machine is limited by both the number of fan‐ins into a given state
and the decisions made in that state.
For example, idle type states can have a large number of
inputs plus increased computational load. With the 4‐input LUT architecture of Speedster22i
FPGAs, once the number of fan
‐ins exceeds four, another level of logic is needed. An easy method to
reduc e the number of fan‐ins is to replicate these states. The duplicated high fan‐in states reduce the
number of inputs, thus reducing the number of levels of logic.