Cypress CY14B101P - Manual (Page 28)

PRELIMINARY CY14B101P
Document #: 001-44109 Rev. *B Page 28 of 32
Hardware STORE Cycle
Parameter Description
CY14B101P
Unit
Min Max
t
DHSB
HSB To Output Active Time when write latch not set 25 ns
t
PHSB
Hardware STORE Pulse Width 15 ns
Figure 30. Hardware STORE Cycle
[9]
~ ~
~ ~
HSB (IN)
HSB (OUT)
SO
RWI
HSB (IN)
HSB (OUT)
RWI
tHHHD
tSTORE
tPHSB
tDELAY
tLZHSB
tDELAY tDHSB tDHSB
tPHSB
HSB pin is driven high to VCC only by Internal
100K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
Write Latch not set
Write Latch set
~ ~
~ ~
~ ~
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