Logic block diagram (cy7c1563v18), Logic block diagram (cy7c1565v18) – Cypress Perform CY7C1561V18 User Manual
Page 3
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
Document Number: 001-05384 Rev. *F
Page 3 of 28
Logic Block Diagram (CY7C1563V18)
Logic Block Diagram (CY7C1565V18)
1M x
1
8
Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS
[1:0]
V
REF
W
rite Add. D
e
co
de
Write
Reg
36
A
(19:0)
20
1M x
1
8
Array
1M x
1
8
Array
1M x
1
8
Array
18
CQ
CQ
DOFF
Q
[17:0]
18
QVLD
18
18
18
Write
Reg
Write
Reg
Write
Reg
5
12K
x
3
6
Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. D
e
cod
e
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
19
144
36
BWS
[3:0]
V
REF
W
rite Add. De
code
Write
Reg
72
A
(18:0)
19
5
12K
x
3
6
Array
5
12K
x
3
6
Array
5
12K
x
3
6
Array
36
CQ
CQ
DOFF
Q
[35:0]
36
QVLD
36
36
36
Write
Reg
Write
Reg
Write
Reg
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