Logic block diagram (cy7c1561v18), Logic block diagram (cy7c1576v18) – Cypress Perform CY7C1561V18 User Manual
Page 2
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
Document Number: 001-05384 Rev. *F
Page 2 of 28
Logic Block Diagram (CY7C1561V18)
Logic Block Diagram (CY7C1576V18)
2M x 8 A
rr
a
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Rea
d
Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
21
32
8
NWS
[1:0]
V
REF
W
rite A
d
d.
Decode
Write
Reg
16
A
(20:0)
21
2M x 8 A
rr
a
y
2M x 8 A
rr
a
y
2M x 8 A
rr
a
y
8
CQ
CQ
DOFF
Q
[7:0]
8
QVLD
8
8
8
Write
Reg
Write
Reg
Write
Reg
2
M
x 9 Arra
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Re
ad Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
9
BWS
[0]
V
REF
W
rite
Add. Decode
Write
Reg
18
A
(20:0)
21
2
M
x 9 Arra
y
2
M
x 9 Arra
y
2
M
x 9 Arra
y
9
CQ
CQ
DOFF
Q
[8:0]
9
QVLD
9
9
9
Write
Reg
Write
Reg
Write
Reg
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