Cypress CY7C1420AV18 - Manual (Page 3)

CY7C1416AV18, CY7C1427AV18
CY7C1418AV18, CY7C1420AV18
Document Number: 38-05616 Rev. *F Page 3 of 31
Logic Block Diagram (CY7C1418AV18)
Logic Block Diagram (CY7C1420AV18)
Write
Reg Write
Reg
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
W
rite Add. Decode
18
21
C
C
18
LD
Control
Burst
Logic
A0
A
(20:1)
R/W
DOFF
1M x
18 Array
1M x 18 Arr
a
y
20
18
DQ
[17:0]
18
CQ
CQ
Write
Reg Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read
A
d
d. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
W
rite Add. Decode
36
20
C
C
36
LD
Control
Burst
Logic
A0
A
(19:1)
R/W
DOFF
512K x 36
Array
512K x
36 Array
19
36
DQ
[35:0]
36
CQ
CQ
[+] Feedback