Rockwell Automation 57C610 Enhanced Basic Language, AutoMax - Manual (Page 137)

CĆ1
Appendix C
Hardware Interrupt Line Allocation
Current Minor Loop (CML) tasks or tasks that use BASIC hardware EVENT
statements require Processors to allocate hardware interrupt lines on the rack
backplane. This is because some portion of task execution depends upon
receiving a userĆdefined hardware interrupt from another module in the rack,
e.g., a Resolver Input module. This appendix will describe the basic method by
which interrupt lines are allocated. See the Control Block Language instruction
manual (JĆ3676) for more information on CML tasks.
Because the number of interrupt lines is limited to four, it is necessary to take
into account the rules by which they are allocated in order to prevent errors
when application tasks are put into run. Each of the four interrupt lines can
service" one of the following:
a)
four BASIC language hardware EVENT statements in BASIC or Control
Block tasks
b) one CML task (used in racks containing drive cards only)
Any one Processor module can allocate one of the four interrupt lines for up to
four EVENT statements and one line for a CML task. (CML tasks are limited to
two per rack because of drive module configuration restrictions.) A minimum of
one hardware interrupt line is allocated for a Processor Module regardless of
whether one or four hardware EVENT statements are used in the application
tasks loaded on that Processor.
The following examples of interrupt line allocation assume that there are two
Processor modules in the rack. Note that these examples do not take into
account the efficiency of distributing application tasks between Processor
modules in this manner (in terms of system performance).
Example #1
x x x x
Slot 1
Processor
Module
Slot 2
Processor
Module
4 hardware EVENT
statements in
BASIC or Control
Block tasks.
No hardware
EVENT statements
or CML tasks.
=ăInterrupt Line
=ăHardware EVENT Statement
=ăCML Task
x
CML