Cs8900a – Cirrus Logic CS8900A User Manual

Page 59

DS271F5

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

Bit 7 Bit 6

0 0 Start transmission after 5 bytes are in the CS8900A
0 1 Start transmission after 381 bytes are in the CS8900A
1 0 Start transmission after 1021 bytes are in the CS8900A
1 1 Start transmission after the entire frame is in the CS8900A

Force

When set in conjunction with a new transmit command, any transmit frames waiting in the trans-

mit buffer are deleted. If a previous packet has started transmission, that packet is terminated
within 64 bit times with a bad CRC.

Onecoll

When this bit is set, any transmission will be terminated after only one collision. When clear, the

CS8900A allows up to 16 normal collisions before terminating the transmission.

InhibitCRC

When set, the CRC is not appended to the transmission.

TxPadDis

When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC

is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes
and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC.

When TxPadDis is set, the CS8900A allows the transmission of runt frames (a frame less than
64 bytes). If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the
CS8900A does not append the CRC

After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.

Notes: The CS8900A does not transmit a frame if TxLength < 3

4.4.12 Register B: Buffer Configuration

(BufCFG, Read/Write, Address: PacketPage base + 010Ah)

Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there is
no interrupt.

001011

These bits provide an internal address used by the CS8900A to identify this as the Buffer Con-

figuration Register.

SWint-X

When set, there is an interrupt requested by the host software. The CS8900A provides the in-

terrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900A acts upon this com-
mand at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1" to this bit.

RxDMAiE

When set, there is an interrupt when a frame has been received and DMA is complete. With

this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set.

Rdy4TxiE

When set, there is an interrupt when the CS8900A is ready to accept a frame from the host for

transmission. (See Section 5.6 on page 99 for a description of the transmit bid process.)

TxUnderruniE

When set, there is an interrupt if the CS8900A runs out of data before it reaches the end of the

frame (called a transmit underrun). When this happens, event bit TXUnderrun (Register C,
BufEvent, Bit 9) is set and the CS8900A makes no further attempts to transmit that frame. If the

RxDMAiE

SWint-X

001011

RxDestiE

Miss OvfloiE

TxCol OvfloiE

Rx128iE

RxMissiE

TxUnder runtiE

Rdy4TxiE