Cs8900a – Cirrus Logic CS8900A User Manual
Page 53
DS271F5
53
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
4.4.5 Register 0: Interrupt Status Queue
(ISQ, Read-only, Address: PacketPage base + 0120h)
The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt
information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s)
in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of
the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register
C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem-
ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See
Section 5.1 on page 78.
Status and Event Bits
Register
F
E
D
C
B
A
9
8
7
6
Number
(Offset)
Name
Interrupt Status Queue
0
(0120h)
ISQ
Reserved (register contents undefined)
2
Extra
data
Runt
CRC
error
Broad-
cast
Individ-
ual Adr
Hashed
RxOK
Dribble
bits
IAHash
4
(0124h)
Rx
Event
Hash Table Index (alternate RxEvent meaning if
Hashed = 1 and RxOK = 1)
Hashed
RxOK
Dribble
bits
IAHash
4
(0124h)
Rx
Eventalt
Reserved (register contents undefined)
6
16coll
Number-of-Tx-collisions
Jabber
Out-of-
Window
TxOK
SQE
error
Loss-of-
CRS
8
(0128h)
TxEvent
Reserved (register contents undefined)
A
Rx
Dest
Rx128
RxMiss TxUnder-
run
Rdy4Tx RxDMA
Frame
SWint
C
(012Ch)
Buf
Event
Reserved (register contents undefined)
E
10-bit Receive Miss (RxMISS) counter, cleared when read
10
(0130h)
RxMISS
10-bit Transmit Collision (TxCOL) counter, cleared when read
12
(0132h)
TxCOL
CRS
Polarity
OK
10BT
AUI
LinkOK
14
(0134h)
LineST
EESize
EL pres-
ent
EEPRO
M OK
EEPRO
Mpresent
SIBUSY
INITD
3.3 V
Active
16
(0136h)
SelfST
Rdy4Tx
NOW
TxBid
Err
18
(0138h)
BusST
Reserved (register contents undefined)
1A
10-bit AUI Time Domain Reflectometer (TDR) counter, cleared when read
1C
(013Ch)
TDR
Reserved (register contents undefined)
1E
7
6
5
4
3
2
1
0
RegContent
RegNum
F
E
D
C
B
A
9
8
RegContent
Table 16. Status and Control Register Descriptions (continued)